The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of magnetic random access memory (MRAM) devices.
Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which use a charge to store information.
A more recent development in memory devices involves spin electronics, which combines semiconductor technology and magnetics. The spin of an electron, rather than the charge, is used to indicate the presence of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. One such spin electronic device is a magnetic random-access memory (MRAM), which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is storable in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment""s alignment. The stored state is read from the element by detecting the component""s resistive state. A memory cell may be constructed by placing the conductive lines and cross-points in a matrix structure having rows and columns.
An advantage of MRAMs compared to traditional semiconductor memory devices such as DRAMs is that MRAMs are non-volatile. For example, a personal computer (PC) utilizing MRAMs would not have a long xe2x80x9cboot-upxe2x80x9d time as with conventional PCs that utilize DRAMs. Also, an MRAM does not need to be powered up and has the capability of xe2x80x9crememberingxe2x80x9d the stored data.
In a cross-point MRAM device, the magnetic memory cells are located between two metal wiring levels. The bottom of the magnetic stacks make electrical contact to a lower wiring level, while the top of the magnetic stacks make electrical contact to an upper wiring level. An alternative MRAM design comprises an offset MRAM device.
In an offset MRAM, conductive lines comprising read lines and write lines are disposed within the same metallization layer. The read lines are connected to each magnetic memory cell. The write lines do not make direct contact to the magnetic memory cells, but rather, a magnetic field for the magnetic memory cells is induced by running electric current through the write lines, which are disposed proximate the magnetic memory cells, in order to influence the magnetic spin direction of the magnetic memory cell, thus writing to the cell.
Preferred embodiments of the present invention achieve technical advantages as a method of manufacturing MRAM offset magnetic memory cells, using double resist layers to pattern either a magnetic stack layer or insulating layer, or both, reducing the number of process steps.
In one embodiment, a method of manufacturing a resistive semiconductor memory device is disclosed. The method includes forming a plurality of first conductive lines, depositing a first insulating layer over the first conductive lines, patterning the first insulating layer with vias to expose at least some of the first conductive lines, and depositing a magnetic stack layer over the first insulating layer and exposed first conductive lines. The magnetic stack layer is patterned to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells. A second insulating layer is deposited over the magnetic memory cells and offset conductive lines. Vias are formed to expose at least some of the magnetic memory cells, and trenches are formed for conductive lines, within the second insulating layer. The method includes filling the vias and trenches within the second insulating layer with a conductive material. At least one of patterning the magnetic stack layer to form magnetic memory cells and offset conductive lines or forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines within the second insulating layer comprise a single etch process.
In another embodiment, a method of manufacturing an MRAM device includes providing a workpiece, depositing a first insulating layer over the workpiece, forming a plurality of first conductive lines within the first insulating layer, and depositing a second insulating layer over the first conductive lines. The method includes patterning the second insulating layer with vias to expose at least some of the first conductive lines, depositing a magnetic stack layer over the second insulating layer and exposed first conductive lines, depositing a first resist over the magnetic stack layer, and patterning and developing the first resist. Portions of the first resist are removed, and a second resist is deposited over the magnetic stack layer and first resist. The second resist is patterned, and the magnetic stack layer is etched in a single etch process to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells. The method includes depositing a third insulating layer over the magnetic memory cells and offset conductive lines, forming vias to expose at least some of the magnetic memory cells and forming trenches for conductive lines within the third insulating layer, and filling the vias and trenches within the third insulating layer with a conductive material.
In another embodiment, a method of manufacturing an MRAM device includes providing a workpiece, depositing a first insulating layer over the workpiece, forming a plurality of first conductive lines within the first insulating layer, and depositing a second insulating layer over the first conductive lines. The method includes patterning the second insulating layer with vias to expose at least some of the first conductive lines, and depositing a magnetic stack layer over the second insulating layer and exposed first conductive lines. The magnetic stack layer is patterned to form magnetic memory cells and offset conductive lines adapted to couple the exposed first conductive lines to the magnetic memory cells. A third insulating layer is deposited over the magnetic memory cells and offset conductive lines, a first resist is deposited over the third insulating layer, and the first resist is patterned and developed. The method includes removing portions of the first resist, depositing a second resist over the third insulating layer and the first resist, and patterning the second resist. The third insulating layer is etched in a single etch process to form vias to expose at least some of the magnetic memory cells and form trenches for conductive lines within the third insulating layer. The vias and trenches within the third insulating layer are filled with a conductive material.
Advantages of embodiments of the invention include reducing the number of process steps required to manufacture an offset MRAM device.